Digital Electronics

Below is the syllabus for Digital Electronics:-

UNIT I

MINIMIZATION TECHNIQUES AND LOGIC GATES

Minimization Techniques: Boolean postulates and laws – De-Morgan’s Theorem, Principle of Duality, Boolean expression – Minimization of Boolean expressions, Minterm, Maxterm, Sum of Products (SOP), Product of Sums (POS), Karnaugh map Minimization – Don’t care conditions, Quine – McCluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive-OR, and Exclusive-NOR- Implementations of Logic Functions using gates, NAND-NOR implementations – Multi-level gate implementations- Multi output gate implementations. TTL and CMOS Logic and their characteristics, Tristate gates.

UNIT II

COMBINATIONAL CIRCUITS

Design procedure – Half adder, Full Adder, Half subtractor, Full subtractor, Parallel binary adder, parallel binary Subtractor, Fast Adder, Carry Look Ahead adder, Serial Adder/Subtractor, BCD adder, Binary Multiplier, Binary Divider, Multiplexer/ De-multiplexer, decoder, encoder, parity checker, parity generators, code converters, Magnitude Comparator.

UNIT III

SEQUENTIAL CIRCUITS

Latches, Flip-flops – SR, JK, D, T, and Master-Slave – Characteristic table and equation, Application table, Edge triggering, Level Triggering, Realization of one flip-flop using other flip-flops, serial adder/subtractor, Asynchronous Ripple or serial counter, Asynchronous Up/Down Counter, Synchronous counters, Synchronous Up/Down counters, Programmable counters, Design of Synchronous counters: state diagram, State table, State minimization, State assignment, Excitation table and maps-Circuit implementation, Modulo-n counter, 555 Timer, Registers – shift registers, Universal shift registers, Shift register counters, Ring counter, Shift counters, Sequence generators.

UNIT IV

MEMORY DEVICES

Classification of memories – ROM: ROM organization, PROM, EPROM, EEPROM, EAPROM, RAM: – RAM organization – Write operation, Read operation, Memory cycle, Timing waveforms, Memory decoding, memory expansion, Static RAM Cell, Bipolar RAM cell, MOSFET RAM cell structure, Dynamic RAM cell structure, Programmable Logic Devices – Programmable Logic Array (PLA), Programmable Array Logic (PAL), Implementation of PLA, PAL using ROM. Introduction to Field Programmable Gate Arrays (FPGA).

TEXTBOOKS

Donald Leach and Albert Paul Malvino, Digital Principles and Applications, 8th Edition, TMH, 2003.M.
Morris Mano, Digital Design, 3rd Edition, Prentice Hall of India Pvt. Ltd., 2003 / Pearson Education (Singapore) Pvt. Ltd., New Delhi,

REFERENCES

K. Maini, Digital Electronics, Wiley India
John Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2006
M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2002.
Salivahanan and S. Arivazhagan, Digital Circuits and Design, 3rd Edition., Vikas Publishing House Pvt. Ltd, New Delhi, 2006
William H. Gothmann, Digital Electronics, 2nd Edition, PHI,
Thomas L. Floyd, Digital Fundamentals, 8th Edition, Pearson Education Inc, New Delhi, 2003
Donald D. Givone, Digital Principles, and Design, TMH,

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